FIG. 1 shows the block diagram of N-bit a Successive Approximation Register Analog-Digital Converter (SAR ADC) comprising Track/Hold, Comparator, N-bit DAC and Binary Search Logic. The analog input voltage VIN is sampled and held by Track/Hold. The Binary Search Logic is initially set to midscale (100 . . . 00). This forces the DAC output VDAC to be VREF/2, where VREF is the reference voltage of ADC. The Comparator compares VIN and VDAC and determines the next operation based on the comparator result. If VIN is greater than VDAC, the comparator output is logic high and the MSB of N-bit register remains at 1. Conversely, if VIN is less than VDAC, the comparator output is logic low and the MSB is cleared to logic 0. This binary-search process proceeds to the next MSB-1 bit and completes once LSB output is obtained.
FIG. 2 shows the exemplary timing diagram of a conventional synchronous 10-bit SAR ADC. The sampling takes 4 clock cycles and binary search takes 10 clock cycles, each conversion requires 14 clock cycles to be finished. For 100 MSPS conversion rate, the clock frequency is 14 times as 1.4 GHz. Such high frequency clock is often not available on the system. Therefore, for higher conversion rate, asynchronous timing scheme or self-time scheme is employed. Asynchronous timing scheme necessitates a fast internally generated clock. An example of the internal self-timing generation of asynchronous scheme is U.S. Pat. No. 9,774,337 issued Sep. 26, 2017, Chao et al, entitled “High Speed SAR ADC Using Comparator Output Triggered Binary Search Timing Scheme And Bit-Dependent DAC Settling”. FIG. 3 illustrates the exemplary timing diagram of asynchronous 10-bit SAR ADC. Half clock cycle time is utilized for the input sampling and half clock cycle is used for 10 binary search bit-tests. The conversion rate equals the input clock rate.
Unlike the bit-test clock has a fixed period in the synchronous scheme, the time period of the asynchronous bit-test clock is not constant since it is generated using delay element. When process speed varies, bit-test clock time period is changing accordingly. FIG. 4 shows the exemplary timing diagram of asynchronous SAR ADC at different process corners. The bit-test clock of slow, typical and fast corners is illustrated. A “done” signal is asserted to indicate that the binary search is complete and the conversion is finished. For the fast process corner, the time delay of delay element is decreased such that the spacing of pulse to pulse is narrowed. The done signal of fast corner is asserted earlier in time than other corners since it finishes bit-test sooner. Specifically, the done signal is asserted at T1, T2 and T3 for slow, typical and fast corners respectively.
The narrower spacing of pulses demands faster DAC settling and Reference settling response. FIG. 5 shows the DAC and Reference settling response of slow and fast process corner respectively. DAC and Reference must settle before the next rising edge of bit-test clock arrives. If DAC or Reference does not settle before the next bit-test arrives, the comparator produces erroneous result and degrades ADC Signal-to-Noise ratio (SNR). The pulse-to-pulse delay Tdly1 of slow process corner is greater than Tdly2 of fast process corner. Therefore, the allowed DAC settling time Tdac settling 2 at fast corner would be shorter than DAC settling time Tdac settling 1 at slow corner. Since the permitted time of fast corner is the most stringent, DAC is required to settle within Tdac settling 2 to ensure the fast corner is working properly. This results in consuming more current or power. In other words, the done signal of fast corner is asserted much earlier than the next sample pulse arrives, this is considered inefficiency since the time of half clock cycle is not fully utilized. ADC is not optimized if the timing is compromised to one specific corner condition.
There are three variables that can affect the time delay: Process, Supply Voltage and Temperature (PVT). For the present integrated circuit (IC) manufacture process, the variation of time delay due to process, voltage and temperature is around 55%, 40% and 15% respectively. Considering the two extreme speed corners, the time delay of slow process, low voltage, and high temperature condition can be two to three times of the time delay of fast process, high voltage, and low temperature condition. Often the time delay is constrained by the slow corner owing to the half clock cycle limit, then the time of fast corner is compromised or not optimized. Note that the time delay of delay element is transconductance over capacitor (gm/c) dependent whereas DAC and Reference delay is resistance capacitance product inverse (1/RC) dependent. Although DAC and Reference responds faster at fast corner, the change over process variation for time delay is more than the change over process variation for DAC and Reference.